Chip Making

Technology Node - WikiChip
How Are Process Nodes Defined? - ExtremeTech
Semiconductor device fabrication - Wikiwand
A process node upgrade is meant to double the number of transistors, hence halving the area, so the distance decrease is square root of 0.5 = 0.7071
90nm -> 65nm -> 45nm -> 32nm -> 22nm -> 14nm -> 10nm -> 7nm -> 5nm
Laser cannot archive required half pitch after 45nm. 3D techniques (FinFET) are used

Die Per Wafer Calculator -

Should You Believe CPU Marketing? - YouTube
gate distance -> cell distance (Pentium III) -> not measuring transistor size anymore (FinFET)
Transistor density is better measure

Intel 10nm Delay Explained & AMD's "7nm" | Ft. David Kanter - YouTube
Intel Ditches "Nanometers," Renames 10nm to "7" & 7nm to "4" - YouTube
14nm and 7nm are NOT what you think it is - Visiting Tescan Part 3/3 - YouTube

Beyond 7nm - the race to 4nm is Samsung's to lose - Android Authority
Samsung Unveils 3nm Gate-All-Around Design Tools - ExtremeTech
FinFET - Wikiwand the transistor became 3D
Tech Brief: FinFET Fundamentals | Lam Research
The 3-D Transistor Transition - YouTube FinFET and Gate All Around (GAA)
FinFET is used for nodes < 28nm

Next-Gen CPUs/GPUs have a HUGE problem! - YouTube SRAM for cache does not scale with process node, and next-gen CPUs/GPUs are using larger cache => greatly increased price; chiplet/tile design help ease this problem for the core and cache can be using different process node

Is a smaller manufacturing process always better? Intel's 10nm SuperFin suggests otherwise | VentureBeat

Packaging

A Brief History of Semiconductor Packaging - YouTube

Plastic Encapsulation
Dual Inline Package (DIP): leads of 2.54mm apart, through hole mounting
Surface Mounting Technology (SMT): smaller leads catered for Very Large Scale Integration (VLSI); allow use of both side of PCB
- Small-Outline Integrated circuit (SOIC): gull-wing leads
- Quad Flat Package (QFP): lead pitch of 0.65 to 1 mm; Shrink QFP, Very Small QFP, Thin QFP variants
- How Motherboards Are Made (2019) | Taiwan Automated Factory Tour, ft. Gigabyte - YouTube fully auto SMT soldering
Pin Grid Array (PGA)
Ball Grid Array (BGA): surface mount version of PGA
Flip Chip: the chip is flipped and wire bonding is ditched
Chip scale packaging: package with a die occupying > 80% of the total packaging area
- Wafer Level Package: die interconnects are hooked up before being cut out of the wafer
Advanced Packaging
chiplets, multi chip modules, hybrid circuits, system in packages, mixing process nodes; TSMC SoIC, 3D IC (different chips stacked), 2.5D IC (chip stacked on interposer)

Advanced Packaging

【亦】唠唠苹果 M1 Ultra：半导体新时代！ - YouTube
Why AMD's Chiplets Work - YouTube

Advanced Packaging Part 1 – Pad Limited Designs, Breakdown Of Economic Semiconductor Scaling, Heterogeneous Compute, and Chiplets
Advanced Packaging Part 2 - Review Of Options/Use From Intel, TSMC, Samsung, AMD, ASE, Sony, Micron, SKHynix, YMTC, Tesla, and Nvidia
Advanced Packaging Part 3 – Intel’s Curious Bet on Thermocompression Bonding, ASM Pacific, Kulicke and Soffa, and Besi TCB Tool Landscape
The Future Of Packaging Gets Blurry – Fanouts, ABF, Organic Interposers, Embedded Bridges – Advanced Packaging Part 4